Perfil (CV) del personal docente investigador

Ibáñez Marín, Pablo Enrique
Departamento: Departamento de Informática e Ingeniería de Sistemas
Área: Arquitectura y Tecnología de Computadores
Centro: Escuela de Ingeniería y Arquitectura

Research Institute: INSTITUTO DE INVESTIGACIÓN EN INGENIERÍA DE ARAGÓN (I3A)
Grupo: T58_17R: GRUPO DE ARQUITECTURA DE COMPUTADORES DE LA UNIZAR(gaZ).

Códigos UNESCO
  • Simulación
  • Arquitectura de ordenadores
Categoría profesional: Prof. Titular Univ.
Página web: http://webdiis.unizar.es/~peimarin/

Formación académica
  • Programa Oficial de Doctorado en Ingeniería Informática. Universidad de Zaragoza. 1998
  • Licenciado en Informática. Universitat Politècnica de Catalunya. 1989

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Artículos

  • Ferrerón, A.; Alastruey-Benedé, J.; Suárez Gracia, D.; Monreal Arnal, T.; Ibáñez Marín, P.; Viñals Yúfera, V. A fault-tolerant last level cache for CMPs operating at ultra-low voltage. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2019

  • Díaz, J.; Monreal, T.; Ibáñez, P.; Llabería, J.M.; Viñals, V. ReD: A reuse detector for content selection in exclusive shared last-level caches. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2019

  • Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez-Marín, Pablo; Viñals-Yúfera, Víctor; Mehmood, Rashid. Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. PLOS ONE. 2019

  • Herruzo, J.M.; Gonzalez Navarro, S.; Ibañez, P.; Viñals Yufera, V.; Alastruey, J.; Plata, O. Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS. 2018

  • Rodríguez-Rodríguez, Roberto; Díaz, Javier; Castro, Fernando; Ibáñez, Pablo; Chaver, Daniel; Viñals, Víctor; Sáez, Juan Carlos; Prieto, Manuel; Piñuel, Luis; Monreal, Teresa; Llabería, José María. Reuse Detector: Improving the management of STT-RAM SLLCs. COMPUTER JOURNAL. 2017

  • Ferreron, A.; Suarez-Gracia, D.; Alastruey-Benede, J.; Monreal-Arnal, T.; Ibañez, P. Concertina: Squeezing in cache content to operate at near-threshold voltage. IEEE TRANSACTIONS ON COMPUTERS. 2016

  • Mikkelsen, C.C.K.; Alastruey-Benedé, J.; Ibáñez-Marín, P.; Risueño, P.G. Accelerating sparse arithmetic in the context of newton’s method for small molecules with bond constraints. LECTURE NOTES IN COMPUTER SCIENCE. 2016

  • Albericio,J.;Ibanez,P.;Vinals,V.;Llaberia,J. M. Exploiting reuse locality on inclusive shared last-level caches. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. 2013

  • Albericio,J.; Gran,R.; Ibáñez,P.; Viñals,V.; Llabería,J. M. ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. 2012

  • Sahelices,B.;de Dios,A.;Ibáñez,P.;Viñals-Yúfera,V.;Llabería,J. M. Effcient handling of lock hand-off in DSM multiprocessors with buffering coherence controllers. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY. 2012

  • Garcia-Risueño,P. ; Ibáñez,P. E. A review of high performance computing foundations for scientists. INTERNATIONAL JOURNAL OF MODERN PHYSICS C. 2012

  • Bosque,A.;Viñals,V.;Ibañez,P.;Llaberia,J. M. Filtering directory lookups in CMPs with write-through caches. LECTURE NOTES IN COMPUTER SCIENCE. 2011

  • Briz Velasco, José Luis; Ramos, Luis M.; Ibáñez, Pablo E.; Viñals, Victor. Multi-level Adaptive Prefetching based on Performance Gradient Tracking. THE JOURNAL OF INSTRUCTION-LEVEL PARALLELISM. 2011

  • Bosque, A.; Viñals, V.; Ibáñez, P.; Llabería, J.M. Filtering directory lookups in CMPs. MICROPROCESSORS AND MICROSYSTEMS. 2011

  • Sahelices, B.; Ibáñez, P.; Viñals, V. ; Llabería, J.M. A methodology to characterize critical section bottlenecks in DSM multiprocessors. LECTURE NOTES IN COMPUTER SCIENCE. 2009

  • Torres, E.;Ibañez,P.;Viñals-Yufera,V.;Llaberia,J. M. Store buffer design for multibanked data caches. IEEE TRANSACTIONS ON COMPUTERS. 2009

  • Ramos, L. M.;Briz,J. L.;Ibañez,P. E.;Viñals,V. Low-Cost Adaptive Data Prefetching. LECTURE NOTES IN COMPUTER SCIENCE. 2008

  • Ramos, Luis M; Briz, José Luis; Ibáñez, Pablo E; Viñals, Víctor. Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH COMPUTER ARCHITECTURE NEWS 2007

  • Alastruey,J.;Briz,J. L.;Ibanez,P.;Vinals,V. Software demand, hardware supply. IEEE MICRO. 2006

  • de Dios,A.;Sahelices,B.;Ibanez,P.;Vinals,V.;Llaberia,J. M. Speeding-Up Synchronizations in DSM Multiprocessors. LECTURE NOTES IN COMPUTER SCIENCE. 2006

  • Torres, E. F.;Ibanez, P.;Vinals, V.;Llaberia, J. M. Contents management in first-level multibanked data caches. LECTURE NOTES IN COMPUTER SCIENCE. 2004

  • Torres, E. F.;Ibanez, P.;Vinals, V.;Llaberia, J. M. Counteracting bank misprediction in sliced first-level caches. LECTURE NOTES IN COMPUTER SCIENCE. 2003



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