Perfil (CV) del personal docente investigador

Suárez Gracia, Darío
Departamento: Departamento de Informática e Ingeniería de Sistemas
Área: Arquitectura y Tecnología de Computadores
Centro: Escuela de Ingeniería y Arquitectura

Research Institute: INSTITUTO DE INVESTIGACIÓN EN INGENIERÍA DE ARAGÓN (I3A)
Grupo: T58_17R: GRUPO DE ARQUITECTURA DE COMPUTADORES DE LA UNIZAR(gaZ).

Códigos UNESCO
  • Unidades centrales y de proceso
Categoría profesional: Profesor contratado doctor
Página web: http://webdiis.unizar.es/~dario/
ORCID: 0000-0002-7490-4067

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Artículos

  • Dávila Guzmán, M.A.; Nozal, R.; Gran Tejero, R.; Villarroya-Gaudó, M.; Suárez Gracia, D.; Bosque, J.L. Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL. JOURNAL OF SUPERCOMPUTING. 2019

  • Ferrerón, A.; Alastruey-Benedé, J.; Suárez Gracia, D.; Monreal Arnal, T.; Ibáñez Marín, P.; Viñals Yúfera, V. A fault-tolerant last level cache for CMPs operating at ultra-low voltage. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2019

  • Valero Bresó, Alejandro; Candel Margaix, Francisco; Suárez Gracia, Darío; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio. An aging-aware GPU register file design based on data redundancy. IEEE TRANSACTIONS ON COMPUTERS. 2019

  • Nunez-Yanez, J.; Amiri, S.; Hosseinabady, M.; Rodríguez, A.; Asenjo, R.; Navarro, A.; Suarez, D.; Gran, R. Simultaneous multiprocessing in a software-defined heterogeneous FPGA. JOURNAL OF SUPERCOMPUTING. 2018

  • Nunez-Yanez, J.; Amiri, S.; Hosseinabady, M.; Rodríguez, A.; Asenjo, R.; Navarro, A.; Suarez, D.; Gran, R. Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. JOURNAL OF SUPERCOMPUTING. 2018

  • Nunez-Yanez, J.; Hosseinabady, M.; Rodríguez, A.; Asenjo, R.; Navarro, A.; Gran-Tejero, R.; Suárez-Gracia, D. Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. ADVANCES IN PARALLEL COMPUTING. 2018

  • Ferreron, A.; Suarez-Gracia, D.; Alastruey-Benede, J.; Monreal-Arnal, T.; Ibañez, P. Concertina: Squeezing in cache content to operate at near-threshold voltage. IEEE TRANSACTIONS ON COMPUTERS. 2016

  • Ortín-Obón, Marta; Suárez-Gracia, Darío; Villarroya-Gaudó, María ; Izu, Cruz; Viñals, Víctor. Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2016

  • Ortín-Obón, Marta; Suárez-Gracia, Darío; Villarroya-Gaudó, María.; Izu, Cruz.; Viñals-Yúfera, Víctor. Analysis of network-on-chip topologies for cost-efficient chip multiprocessors. MICROPROCESSORS AND MICROSYSTEMS. 2016

  • Cascaval, Calin; Montesinos Ortego, Pablo; Robatmili, Behnam ; Suárez Gracia, Darío. Concurrency in Mobile Browser Engines. IEEE PERVASIVE COMPUTING. 2015

  • Ferrerón,A.; Suárez-Gracia,D.; Alastruey-Benede,J.; Monreal,T.; Viñals,V. Block disabling characterization and improvements in CMPs operating at ultra-low voltages. PROCEEDINGS (SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING). 2014

  • Ortín, M.; Suárez, D.; Villarroya, M.; Izu, C.; Viñals, V. Dynamic construction of circuits for reactive traffic in homogeneous CMPs. PROCEEDINGS - DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION. 2014

  • Suárez Gracia, Darío; Ferrerón, Alexandra; Montesano del Campo, Luis; Monreal Arnal, Teresa; Viñals Yúfera, Víctor. Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. 2014

  • Ferreron-Labari,A.;Ortin-Obon,M.;Suarez-Gracia,D.;Alastruey-Benede,J.;Vinals-Yufera,V. Shrinking L1 instruction caches to improve energy-delay in SMT embedded processors. LECTURE NOTES IN COMPUTER SCIENCE (INCLUDING SUBSERIES LECTURE NOTES IN ARTIFICIAL INTELLIGENCE AND LECTURE NOTES IN BIOINFORMATICS). 2013

  • Suárez Gracia,D.;Dimitrakopoulos,G.;Monreal Arnal,T.;Katevenis,M. G. H.;Viñals Yufera,V. LP-NUCA: Networks-in-cache for high-performance low-power embedded processors. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2012

  • Muzahid, Abdullah; Suárez, Dario; Qi, Shanxiang; Torrellas, Josep. SigRace: Signature-based Data Race Detection. SIGARCH COMPUTER ARCHITECTURE NEWS 2009

  • Suarez, D.;Monreal,T.;Vallejo,F.;Beivide,R.;Viñals,V. Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap. PROCEEDINGS - DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION. 2009

Comunicaciones

  • Tabik, S.; Ortega, G.; Garzón, E. M.; Suárez, D. A data partitioning model for highly heterogeneous systems. LECTURE NOTES IN COMPUTER SCIENCE (INCLUDING SUBSERIES LECTURE NOTES IN ARTIFICIAL INTELLIGENCE AND LECTURE NOTES IN BIOINFORMATICS). 2017



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