Perfil (CV) del personal docente investigador

Ibáñez Marín, Pablo Enrique
Departamento: Departamento de Informática e Ingeniería de Sistemas
Área: Arquitectura y Tecnología de Computadores
Centro: Escuela de Ingeniería y Arquitectura

Research Institute: INSTITUTO DE INVESTIGACIÓN EN INGENIERÍA DE ARAGÓN (I3A)
Grupo: T58_23R: gaZ: grupo de Arquitectura de Computadores de la Universidad de Zaragoza

Códigos UNESCO
  • Simulación
  • Arquitectura de ordenadores
Categoría profesional: Prof. Titular Univ.
Página web: http://webdiis.unizar.es/~peimarin/

Titulaciones universitarias
  • Licenciado en Informática. Universitat Politècnica de Catalunya. 1989

Doctorados
  • Programa Oficial de Doctorado en Ingeniería Informática. Universidad de Zaragoza. 1998

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Artículos

  • López-Villellas, L.; Kjelgaard Mikkelsen C. Ch.; Galano-Frutos, J. J.; Marco-Sola, S.; Alastruey-Benedé, J.; Ibáñez, P.; Moretó, M.; Sancho, J.; García-Risueño, P. Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code. COMPUTER PHYSICS COMMUNICATIONS. 2023. DOI: 10.1016/j.cpc.2023.108742

  • Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Viñals-Yúfera, Víctor. Balancer: bandwidth allocation and cache partitioning for multicore processors. JOURNAL OF SUPERCOMPUTING. 2023. DOI: 10.1007/s11227-023-05070-0

  • Escuin, Carlos; Ibáñez, Pablo; Navarro, Denis; Monreal, Teresa; Llabería, José M.; Viñals, Víctor. L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime. PLOS ONE. 2023. DOI: 10.1371/journal.pone.0278346

  • Langarita, Rubén; Armejach, Adrià; Ibáñez, Pablo; Alastruey-Benedé, Jesús; Moretó, Miquel. Porting and optimizing BWA-MEM2 using the Fujitsu A64FX processor. IEEEACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS. 2023. DOI: 10.1109/TCBB.2023.3264514

  • Navarro-Torres, Agustin; Panda, Biswabandan; Alastruey-Benede, Jesus; Ibañez, Pablo; Viñals-Yufera, Victor; Ros, Alberto. Berti: an Accurate Local-Delta Data Prefetcher. PROCEEDINGS OF THE ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO. 2022. DOI: 10.1109/MICRO56248.2022.00072

  • Langarita, Ruben; Armejach, Adria; Setoain, Javier; Ibanez-Marin, Pablo; Alastruey-Benede, Jesus; Moreto, Miquel. Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. IEEEACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS. 2022. DOI: 10.1109/TCBB.2020.3000253

  • Valero, Alejandro; Gran-Tejero, Rubén; Suárez-Gracia, Darío; Georgescu, Emanue A.; Ezpeleta, Joaquín; Álvarez, Pedro; Muñoz, Adolfo; Ramos, Luis M.; Ibáñez, Pablo. A learning experience toward the understanding of abstraction-level interactions in parallel applications. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2021. DOI: 10.1016/j.jpdc.2021.05.008

  • Díaz, J.; Ibáñez, P.; Monreal, T.; Viñals, V.; Llabería, J.M. Near-optimal replacement policies for shared caches in multicore processors. JOURNAL OF SUPERCOMPUTING. 2021. DOI: 10.1007/s11227-021-03736-1

  • Herruzo, J.M.; Gonzalez Navarro, S.; Ibañez, P.; Viñals Yufera, V.; Alastruey, J.; Plata, O. Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. IEEEACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS. 2020. DOI: 10.1109/TCBB.2018.2884701

  • Navarro-Torres, Agustín; Alastruey-Benedé, Jesús; Ibáñez-Marín, Pablo; Viñals-Yúfera, Víctor. Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. PLOS ONE. 2019. DOI: 10.1371/journal.pone.0220135

  • Ferrerón, A.; Alastruey-Benedé, J.; Suárez Gracia, D.; Monreal Arnal, T.; Ibáñez Marín, P.; Viñals Yúfera, V. A fault-tolerant last level cache for CMPs operating at ultra-low voltage. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2019. DOI: 10.1016/j.jpdc.2018.10.010

  • Díaz, J.; Monreal, T.; Ibáñez, P.; Llabería, J.M.; Viñals, V. ReD: A reuse detector for content selection in exclusive shared last-level caches. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. 2019. DOI: 10.1016/j.jpdc.2018.11.005

  • Rodríguez-Rodríguez, Roberto; Díaz, Javier; Castro, Fernando; Ibáñez, Pablo; Chaver, Daniel; Viñals, Víctor; Sáez, Juan Carlos; Prieto, Manuel; Piñuel, Luis; Monreal, Teresa; Llabería, José María. Reuse Detector: Improving the management of STT-RAM SLLCs. COMPUTER JOURNAL. 2017. DOI: 10.1093/comjnl/bxx099

  • Ferreron, A.; Suarez-Gracia, D.; Alastruey-Benede, J.; Monreal-Arnal, T.; Ibañez, P. Concertina: Squeezing in cache content to operate at near-threshold voltage. IEEE TRANSACTIONS ON COMPUTERS. 2016. DOI: 10.1109/TC.2015.2479585

  • Mikkelsen, C.C.K.; Alastruey-Benedé, J.; Ibáñez-Marín, P.; Risueño, P.G. Accelerating sparse arithmetic in the context of newton’s method for small molecules with bond constraints. LECTURE NOTES IN COMPUTER SCIENCE. 2016. DOI: 10.1007/978-3-319-32149-3_16

  • Albericio,J.;Ibanez,P.;Vinals,V.;Llaberia,J. M. Exploiting reuse locality on inclusive shared last-level caches. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. 2013. DOI: 10.1145/2400682.2400697

  • Garcia-Risueño,P. ; Ibáñez,P. E. A review of high performance computing foundations for scientists. INTERNATIONAL JOURNAL OF MODERN PHYSICS C. 2012. DOI: 10.1142/S0129183112300011

  • Sahelices,B.;de Dios,A.;Ibáñez,P.;Viñals-Yúfera,V.;Llabería,J. M. Effcient handling of lock hand-off in DSM multiprocessors with buffering coherence controllers. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY. 2012. DOI: 10.1007/s11390-012-1207-2

  • Albericio,J.; Gran,R.; Ibáñez,P.; Viñals,V.; Llabería,J. M. ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. 2012. DOI: 10.1145/2086696.2086698

  • Briz Velasco, José Luis; Ramos, Luis M.; Ibáñez, Pablo E.; Viñals, Victor. Multi-level Adaptive Prefetching based on Performance Gradient Tracking. THE JOURNAL OF INSTRUCTION-LEVEL PARALLELISM. 2011

  • Bosque, A.; Viñals, V.; Ibáñez, P.; Llabería, J.M. Filtering directory lookups in CMPs. MICROPROCESSORS AND MICROSYSTEMS. 2011. DOI: 10.1016/j.micpro.2011.08.006

  • Bosque,A.;Viñals,V.;Ibañez,P.;Llaberia,J. M. Filtering directory lookups in CMPs with write-through caches. LECTURE NOTES IN COMPUTER SCIENCE. 2011. DOI: 10.1007/978-3-642-23400-2_26

  • Torres, E.; Ibañez, P.; Viñals-Yufera, V.; Llaberia, J.M. Store buffer design for multibanked data caches. IEEE TRANSACTIONS ON COMPUTERS. 2009. DOI: 10.1109/TC.2009.57

  • Sahelices, B.; Ibáñez, P.; Viñals, V. ; Llabería, J.M. A methodology to characterize critical section bottlenecks in DSM multiprocessors. LECTURE NOTES IN COMPUTER SCIENCE. 2009. DOI: 10.1007/978-3-642-03869-3_17

  • Ramos, L. M.;Briz,J. L.;Ibañez,P. E.;Viñals,V. Low-Cost Adaptive Data Prefetching. LECTURE NOTES IN COMPUTER SCIENCE. 2008

  • Ramos, Luis M; Briz, José Luis; Ibáñez, Pablo E; Viñals, Víctor. Data prefetching in a cache hierarchy with high bandwidth and capacity. ACM SIGARCH COMPUTER ARCHITECTURE NEWS. 2007. DOI: 10.1145/1327312.1327319

  • Alastruey,J.;Briz,J. L.;Ibanez,P.;Vinals,V. Software demand, hardware supply. IEEE MICRO. 2006

  • de Dios,A.;Sahelices,B.;Ibanez,P.;Vinals,V.;Llaberia,J. M. Speeding-Up Synchronizations in DSM Multiprocessors. LECTURE NOTES IN COMPUTER SCIENCE. 2006

  • Torres, E. F.;Ibanez, P.;Vinals, V.;Llaberia, J. M. Contents management in first-level multibanked data caches. LECTURE NOTES IN COMPUTER SCIENCE. 2004

  • Torres, E. F.;Ibanez, P.;Vinals, V.;Llaberia, J. M. Counteracting bank misprediction in sliced first-level caches. LECTURE NOTES IN COMPUTER SCIENCE. 2003



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